This invention relates to time domain filtering and filters that make use of charge sharing techniques.
Time domain filters are generally classified as either finite impulse response filters (FIR filters) or infinite impulse response filters (IIR filters). FIR filters compute their output signals based solely on a finite history of values of the input signal while IIR filters compute their output signals based on values of the input signal and previous values of the output signal (i.e., IIR filters are recursive).
Conventional digital time domain filters receive a digitized, discrete-time (e.g., sampled) input signal and generate a digitized, discrete-time output signal which includes an altered version of the sampled input signal. Such filters are generally implemented using digital hardware such as dedicated digital signal processing chips (DSPs). Various designs of such filters and their associated advantages, disadvantages, and applications are well known in the art and are not further discussed in this application.
Discrete time, or more generally discrete sample (e.g., spatial sample), time domain filtering has been implemented using analog signals. For example, a wide range of what are often referred to as “switched capacitor” filters are used, generally making use of a technique of charge transfer using active amplifier stages, whereby a signal represented by charge on capacitive elements at an input of an amplifier stage is transferred to charge on capacitive elements at an output of the amplifier stage. An advantage of circuitry that directly processes analog signals is avoiding the need to convert the signal levels to digital form and reduced circuit resources required to process the signal levels in analog form and/or higher clocking rates, as compared to use of a digital arithmetic unit of digital signal processor.
Another approach to discrete time analog signal processing makes use of active elements for combining analog signals. For example, one approach to implementing a finite impulse response filter is to use a capacitor array (e.g., a tapped delay line) to store signal values, and a set of analog multipliers with controllable gain that scale the voltages at the outputs of the array, and/or integrators prior to combination to determine the output of the filter.